1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a bump structure in flip chip bonding or an electrode structure of a semiconductor device.
2. Related Art
Recently, computer and other electronic instruments have been demanded to be higher integrated and mounted at a higher density for cost reduction. Along this trend, the flip chip mounting method has been in the limelight for the comparatively higher bonding strength and possible high-density mounting. In the flip chip mounting technique, a semispherical electrode (bump) is formed on the electrode lead part of a semiconductor element, a wiring pattern is formed in correspondence with the bump on an external substrate (hybrid IC substrate), and both the bump and the external substrate having the wiring pattern are disposed in opposition to each other and soldered to each other.
The bump inevitably becomes smaller when a semiconductor chip is miniaturized. As a bump of such structure, a technique disclosed in the Japanese Unexamined Patent Publication No. 4-217323 is known, in which Ti is formed by the sputtering method as a barrier metal on the lead of the electrode, and then a bump material is formed thereon by the evaporation method or the plating method.
However, in this case, when the work in process is subjected to heat treatment within a mixed gas with hydrogen and nitrogen in the secondary process to improve the electric characteristics, there is a problem that the Ti is made embrittlement due to hydrogen annealing and the mechanical strength of the bump is degraded.
Furthermore, as disclosed in the Japanese Unexamined Patent Publication No. 4-217323, the structure in which Ti is used for the barrier metal has a problem that the barrier metal is over-etched or under-etched due to uneven etching time, and this causes dispersion in the bump diameter, and as a result, there is dispersion in the bump strength. For example, FIG. 9 illustrates the relationship between the bump diameter and the bump strength. It is understood from FIG. 9 that, when the bump diameter varies from 220 .mu.m to 160 .mu.m, the bump strength lowers to about a half the strength thereof down from 300 gf/bump. When the bump diameter is downsized to 50 .mu.m, the bump strength lowers to approximately 15 gf/bump.
If the bump diameter disperses by .+-.10 .mu.m from 160 .mu.m and 50 .mu.m respectively due to etching and the strength when the bump diameters are 160 .mu.m and 50 .mu.m is supposed to be 1 in index, dispersions in the strength when the dump diameters are 160 .mu.m and 50 .mu.m are ones as illustrated in FIG. 10. That is, if the bump diameter has a dispersion of .+-.10 .mu.m from 160 .mu.m due to etching, the bump strength varies within a small range from 0.88 to 1.12 in index. However, if the bump diameter has a dispersion of .+-.10 .mu.m from 50 .mu.m, the bump strength has a large dispersion from 0.64 to 1.44 in index.
In LSI, for higher integration and higher-density mounting of electronic instruments, the miniaturization of wiring has drawn much attention, and Cu wiring having a low resistance for wiring materials and a high resistance to electromigration has drawn much attention as reported in, for example, Mori et al., "Electromigration endurance in TiWN/Cu/TiWN interconnection", (Proceedings of the 55th meeting of the Applied Physics Association of Japan, 1994, p.617, 19a-ZD-9).
On other hand, when Cu is used for the wiring, there is a problem that the adhesiveness to the barrier metal is so low that exfoliation may be caused as reported in, for example, Furuya et al., "Estimation of adhesivity between Cu and barrier metals by contact angle measurement", (Proceedings of the 55th meeting of the Applied Physics Association of Japan, 1994, p.725, 21p-ZD-5).